In many electronic applications, particularly portable electronic devices such as mobile communication devices, reducing power consumption is one of the key requirements in the respective integrated circuit design. One of the methods for reducing power consumption is using dual operation mode, in which the normal operation of the integrated circuit may use normal operation voltage VDD, which is high enough to drive the integrated circuit to achieve required high performance. In operations not demanding in the area of performance, a reduced operation voltage (data-retention voltage, also sometimes known as gated-VDD) may be used to provide power to the integrated circuits. Under the data-retention voltage that is lower than operation voltage VDD, less power is consumed. The data-retention voltage, although causing degradation in the performance of the integrated circuit, is not an issue in certain operations, such as in the power down mode or standby mode.
Conventionally, the data-retention voltage is provided by embedded voltage regulators, which are embedded in memory macros. FIG. 1 illustrates a conventional circuit capable of providing operation voltage VDD and a data-retention voltage. Power supply line 100 carries operation voltage VDD. PMOS transistors P1 and P2 are used to control whether operation voltage VDD or the data-retention voltage is supplied to memory macro 102. By supplying a low voltage to the gate of PMOS transistor P1 and a high voltage to the gate of PMOS transistor P2, operation voltage VDD is provided to the SRAM periphery logic and cell array in memory macro 102. Conversely, by supplying a high voltage to the gate of PMOS transistor P1 and a low voltage to the gate of PMOS transistor P2, the data-retention voltage, which equals voltage VDD minus the voltage drop on diode D1, is provided to the SRAM periphery logic and cell array in memory macro 102. In FIG. 1, diode D1 acts as an embedded voltage regulator.
The conventional circuit, however, suffers from drawbacks. The voltage-drop Vdiode and the data-retention voltage are affected by process variations and temperature variations. For example, the data-retention voltage gated-VDD of one circuit working at a slow-slow (SS) process corner (meaning both PMOS and NMOS transistors have low performance and low power consumption) may have its data-retention voltage equal to a first value. Another circuit having the same circuit design but working at a fast-fast (FF) process corner (meaning NMOS transistors and PMOS transistors are fast) however, will have a data-retention voltage having a second value different from the first value. The variation in the data-retention voltage may incur one of two consequences. If the data-retention voltage is too high, the leakage current of memory macro 102 will be high, and hence the purpose of having the data-retention voltage is defeated. If the data-retention voltage is too low, the data stored in memory macro 102 may be lost.
In addition, the voltage drop Vdiode on diode D1 is also related to the current Idiode flowing through diode D1, and a fluctuation in current Idiode causes a fluctuation in voltage drop Vdiode, and vice versa. Therefore, the data-retention voltage varies when the current Idiode flowing through diode D1 fluctuates. Further, current Idiode is determined by the leakage current of memory macro 102. Accordingly, different memory macros having different designs, for example, different sizes may have different leakage currents, which in turn affects current Idiode and voltage drop Vdiode. This means that to reduce the effect of current Idiode on voltage drop Vdiode, voltage regulators that are more complicated than simple diodes may be needed. What is needed, therefore, is a method and structure for overcoming the above-described shortcomings in the prior art.